2.5D X-Clock Tree Synthesis Based on Voltage-Island Combination for Reducing Power and Delay

For the current nanometer process technology, a SoC (system-on a chip) integrates a number of different functional modules and usually has multimode operations for different set of modules that work at different time periods. If all the modules are supported with a uniform supplying voltage, the power always consumed the same during all the working time. To save the power, the voltage-island design methodology [1] assigns multiple supply voltages (MSV) to the functional modules of a SoC. The performance-critical modules are assigned the highest supplying voltage for keeping the high speed requirement with paying more power consumption. Other noncritical-based modules can operate at different lower voltages for no requiring the speed by paying less power. Thus, the power and speed can be trade off in a SoC.

The 3D stacked IC technology has replaced the design of 2D SoC. The imaginary advantages of adopting 3D technology are to shorten their interconnections with inserting many TSVs (Through-silicon via) and to promote the chip performance [2]. For a 3D IC, the MSV design can support multiple voltages that form a number of voltage islands for managing the usage of power consumption. The clock network in the voltage islands of a 3D IC is thus more complex and difficult. The problem of a 3D clock tree construction with the minimization of power consumption and clock delay will be challenge.

Relating voltage-island various works were addressed for 2D or 3D SoC designs. Lee et al. [3] proposed the voltage-island partitioning and floorplanning under the control for timing constraints. Dong and Goto [4] presented the floorplanning approach based on the multi-voltage and level-shifter driven. A global routing for multi-voltage islands based on powerdriven approach [5] was proposed for the evaluation of power reduction. Lee et al. [6] proposed the voltage-island-based floorplanning with considering the optimization of reducing power consumption and temperature.

In addition, many literatures [7,8,9] were concentrated on single voltage island for clock tree construction. Tsai et al. [10] proposed a clock tree construction on multimode multivoltage islands. With the binary clustering approach, they inserted buffers and adjusted their locations to minimize the clock delay and clock skew for matching different operated modes. Lin et al. [11] improved the above approach by replacing some inserted buffers with adjustable delay buffers (ADBs) for the well-defined control to the clock delay under the boundary skew. Kim [12] expanded the clock tree synthesis to a 3D stacked IC. With the requirement of zero skew, the clock tree construction depends on the trade-off of TSVs and total wire length. The deferred layer embedding (DLE) is used for reducing the number of TSVs while the deferred merge embedding is employed for minimizing the total wire length. Chen et al. [13] proposed the 3D-IC clock tree that constructs the clock tree on ASIC layer to associate with the pre-defined clock network on platform layer. The TSVs on ASIC layer projected from the platform layer were controlled for minimizing the clock delay and skew. Wang et al. [14] presented the prebond testability for two individual clock trees on respective upper and bottom layers and then combined them by inserting TSVs and TSV buffers to form a 3D clock tree.