At-Speed test Prominence
Abstract
With the remarkable scaling down of technology, test engineers are encountered with new challenges. With the reduction technology moving down to Deep Submicron level, the digital designs are moving closer to the probability of defects related to time. The traditional Stuck-at tests and IDDQ tests can no more detect few distinctive faults which may be occurring due to issues related to timing of the signal. The defect spectrum is thus broadened by the inclusion of other types of faults such as high impedance shorts, in-line resistance, and cross-talk between signals. This paper proposes the use of AtSpeed test which is better suited to detect the new types of failures that occur in a digital circuit due to its complex design. The use of At-speed test ensures the timing reliability of the chip after manufacturing thereby reducing DPM (Defect per million) rate. At-speed tests when added with the traditional stuck-at tests, guarantees maximum fault coverage and reduced DPM rates (@30 to 70%). Though At-speed testing is not a new concept and few ASIC vendors have been using this, they have been using functional test patterns to create them which are a very tedious and time consuming routine. Diagnosing the failure source also becomes difficult with the failure of functional patterns. This paper discusses about the fault models provided by industries leading ATPG tools that targets the At-speed failure.
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Introduction
A physical defect within a circuit or a system is termed as Fault. A fault may cause a system failure or sometimes may not affect the system at all and goes unnoticeable. A fault that results in an incorrect state of the circuit generates an Error. This error deviates the entire system to work as per its specified design and the design fails in its functionality. This is called the failure of the system. Hence the failure of a system is caused by an error in the circuit and the root cause of this error may be a small fault in the smaller abstraction levels of the circuit. Thus identifying and fixing every single fault is very important. A scan test using Automatic Test Pattern Generation (ATPG) is done which detects any manufacturing defects in the circuit. The Test operates on two modes, A shift mode and Capture mode. In the shift mode, all sequential elements are connected as shift registers. This mode is used to control the circuit and observe the result. Whereas in the capture mode, the values stored in the sequential elements are propagated from the source and through the functional logic to the sink.
Conclusion
We have several other new genres of defect arising due to nanometre process. Thus using only conventional testing approaches may put companies into high risk of increase in DPM levels. At-speed testing is the best solution. LOS and LOC approaches and their pros and cons are discussed. With the help of pipelined scan enable, the difficulties in LOS approach are rendered thus allowing users to assess the trade-offs between the two approaches and decide and plan the best solution for them.