Implementation of AES algorithm
Abstract
Data security has become one of the most important concerns in the recent times. This has led to an increase in the importance of cryptography of the electronic data. Cryptography is the process of protecting digital information. Though there are numerous encryption systems used in security systems by various organizations, for the wider use, a particular encryption method is used as a standard. The internationally accepted and acclaimed algorithm is Advanced Encryption Standard (AES). Here in this design we are implementing the Advanced Encryption Standard (AES) with a key length of 128 bits using Verilog hardware description language (HDL)
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Introduction
Each day milllions of people generate enormous amounts of data in various fields such as banking , financial services , telecommunication etc. it is very important to not only keep this data secure during transmission but also during storage. In this regard cryptogrphy provides a method to be able to rely on the data and keep it secure from the attackers.
For a long time Data encryption standard(DES) was the standard for the symmetric key encryption.It has key length of 56 bits. This key length is small and could easily be attacked. The National Institute of Standards and Technology (NIST) thus called for a proposal for a new advanced encryption standard. Selection of AES was an open process. In 2001 NIST declared the block cipher Rijndael as the new AES.
AES takes an input data stream of 128 bits and encrypts it to give the output cipher of 128 bits. It supports 3 different key lengths and with each key different no. of rounds are associated. For a 128 bit key there are 10 rounds, with 192 bit key 12 rounds and with 256 bit key there are 14 rounds.
Wireless Local Area Networks (WLAN), Wireless Personal Area Networks (WPAN), Wireless Sensor Networks (WSN), Smart Cards ,the Wi-Fi encryption standard IEEE 802.11i, the secure shell network protocol SSH (Secure Shell), the Internet phone Skype are examples of a few technologies where AES is used.
Conclusion
Although software implementations leads to smaller requirement of resources but high performance and speed can be achieved by hardware implementations. An efficient implementation of AES was done which resulted in lower no. of slices required for implementation. The efficiency and performance was made to increase. Thus reusability of resources can lead to better results. Simulation of AES algorithm was done on ModelSim software and implemented on Xilinx XC3S500E Spartan-3E FPGA kit.